In the field of integrated circuit processing, and the sub-field of statistical analysis and circuit yield, it is continually more important to accurately measure and understand the statistical variation of devices and interconnections. Variations in these quantities occur as a result of the IC manufacturing process—variations in the composition of the materials that make up the devices and in the dimensions of the devices. An important component of this understanding is the relative influence of systematic and random contributions to the net variation.
It is well known that there is variation across an integrated circuit chip of the composition of the materials used to form the IC and also the dimensions of devices and connections. For example, CVD deposition is not uniform across a chip and less uniform across a wafer, in spite of determined efforts by process engineers to achieve perfect uniformity. As another example, the lithography process does not produce geometric figures (lines, rectangles, etc.) that are perfectly uniform across a chip or wafer.
As a result, transistors and other devices are not uniform across a chip and their switching speed, transit time, switching voltage and other parameters will not be uniform. Further, the performance of devices, sub-circuits etc. will not be uniform even when the systematic variation has been reduced as much as possible, and there will be random statistical fluctuations in operating parameters.
These random fluctuations can be caused by the stochastical distribution of dopants varying the amount of impurities within the channel of semiconductors transistors, the roughness of the injecting edges in the transistor junction causing very local channel length variations and the topography of the thickness variation of the gate oxide.
In the course of designing a circuit, it is necessary to calculate the time at which signals arrive, e.g. all the inputs to an AND circuit must arrive at the same time (within a margin of error). It is also important to calculate possible failures caused by systematic errors in the thickness of a film layer or in the amount of dopant in a component.
A simple approach in the past has been to make pessimistic assumptions, similar to a worst-case scenario. As technology improves and the demands of space limitations become more stringent, this approach becomes less tenable and it is more important that the estimates be accurate.
The variation of a parameter will depend on both systematic variations that depend on non-uniform concentration of dopant, film thickness and the like and random statistical fluctuations. The random variations will tend to cancel out when a number of steps are performed in a calculation to get a result.
Thus, simply adding up variations will produce a pessimistic result that is wasteful in that a greater timing margin (or other margin in film thickness and the like) is used in the design than is necessary. A more accurate result that exploits resources more efficiently can be achieved if the random and system sources of variation are well known.
The art could benefit from a test structure and method to improve the accuracy of estimates of random and systematic errors in integrated circuit parameters.